1. Field of the Invention
The present invention relates to phase locked loop (PLL) circuits, and more specifically to a method and apparatus for generating a lock signal indicating whether an output clock signal generated by a PLL is locked to an input reference signal.
2. Related Art
Phase locked loop (PLL) circuits are often used to generate output clock signals synchronous with an input reference signal. Typically, a desired frequency (often in the form of a multiple of the frequency of the input reference signal) of an output clock signal is specified, and a PLL generates the output clock signal with the specified frequency.
An output clock signal (or PLL) is generally said to be locked when an output clock signal has acquired a specified frequency and tracks the input reference signal. A lock situation is often detected by dividing the output clock signal with a multiple (of the input reference signal) used to specify the desired frequency, and comparing the phase and frequency of the resulting divided signal with the input reference signal. A lock would be found to exist if a match is detected between the two compared signals in terms of both phase and frequency for a sufficiently long time.
Lock signal generation circuits are often employed in (or associated with) PLLs. A typical lock signal generation circuit provides a signal indicating whether the PLL is locked, and the signal is often used to determine whether to provide the output clock signal to external circuits (which are typically driven by the output clock signal).
Lock signal generation circuits generally need to be designed meeting several requirements. One typical requirement is that a lock be indicated when the PLL is accurately locked. Another typical requirement is that the lock (or unlock) indications not be susceptible to short term disturbances such as jitter in the input reference signal.
Therefore, what is generally needed is a lock signal generation method and apparatus which meets such requirements.